The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to circuits and methods of generating internal clocks for synchronous memory devices.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to a decoded external address, and an address decoder circuit coupled to the row and column decoder circuits for decoding the external address.
There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can repeatedly write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which generally only permits the user in routine operation to read data already stored on the ROM. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM generally cannot be written to in routine operation. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modem PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAMs can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
In synchronous system memories, an external clock signal drives individual synchronous memory devices in the system, and the synchronous memory devices perform specific data transfer operations, typically in response to the rising edges of the external clock signal. In a typical synchronous memory device, such as an SDRAM, a processor or some other external circuit applies address, data and transfer command information to the synchronous memory device. The synchronous memory device latches the address and command information on a particular rising edge of the external clock signal, and the processor knows that, at a predetermined number of clock cycles later, data may be read from the addressed synchronous memory device. During such data transfers, a clock generator circuit in the synchronous memory device develops an internal clock signal in response to the external clock signal, and the various components within the synchronous memory device are controlled in response to the internal clock signal. The clock generator circuit typically includes a one-shot circuit that operates to develop the internal clock signal in response to the external clock signal.
In modern system memories, the frequency of the external clock signal is ever increasing to enable data transfer to and from the synchronous memory devices at correspondingly faster rates. As the external clock frequency increases, operation of the one-shot circuit becomes more critical due to the corresponding frequency increase of the internal clock signal that must be developed by the one-shot circuit. Delays in recovery of the one-shot circuit may cause the one-shot circuit to miss the next rising edge of the external clock, thus causing a failure of the internal clock.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate circuits and methods of generating internal clock signals for synchronizing commands in a synchronous memory device.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Various embodiments utilize clock generator circuits containing a delay circuit having at least one delay element and at least one bypass. These elements are arranged to activate the bypass in response to a first logic level presented at the input of the delay circuit and to deactivate the bypass in response to a second logic level presented at the input of the delay circuit. Such clock generators are useful in synchronous memory devices for generating internal clock signals of fixed pulse width from an external clock signal. The internal clock signal is generated from a triggering event, such as a rising edge of the external clock signal, and has a pulse width determined by the delay time of the delay elements. The first logic level may be generated in response to the beginning of an output pulse of the clock generator while the second logic level may be generated in response to the completion of an output pulse of the clock generator. Bypassing the delay element upon completion of an output pulse more quickly prepares the clock generator to receive the next triggering event.
For one embodiment, the invention provides a clock generator. The clock generator includes an input buffer for receiving an external clock signal and a one-shot circuit coupled to the input buffer for providing output pulses in response to the external clock signal. The one-shot circuit includes a delay circuit having at least one delay element and at least one associated bypass. The one-shot circuit generates a first logic level in response to a completion of an output pulse and presents the first logic level to an input of the delay circuit. The first logic level activates the at least one associated bypass and propagates across each delay element substantially without delay. The one-shot circuit further generates a second logic level in response to a beginning of an output pulse and presents the second logic level to the input of the delay circuit. The second logic level deactivates the at least one associated bypass and is passed to the output of the delay circuit at a time delta equal to or greater than a predetermined delay time of the at least one delay element.
For another embodiment, the invention provides a clock generator. The clock generator includes an input buffer for receiving an external clock signal and a one-shot circuit coupled to the input buffer for providing output pulses in response to the external clock signal. The one-shot circuit includes a NAND SR latch having a set input, a reset input and an output. The set input is coupled to an output of the input buffer and an output pulse is provided on the output of the SR latch. The one-shot circuit further includes a delay circuit having an input and an output. The output of the delay circuit is coupled to the reset input of the SR latch. The input of the delay circuit is coupled to receive a first logic level indicative of a completion of an output pulse and to receive a second logic level indicative of a beginning of an output pulse. The delay circuit includes at least two delay elements coupled in series between the input and the output of the delay circuit and having a predetermined delay time, and at least two bypasses. Each bypass is associated with one delay element in a one-to-one relationship. Furthermore, each bypass is activated in response to the first logic level, thereby passing the first logic level across each delay element substantially without delay, and deactivated in response to the second logic level, thereby passing the second logic level from the input of the delay circuit to the output of the delay circuit at a time delta substantially equal to or greater than the predetermined delay time of the at least two delay elements.
For a further embodiment, the invention provides a memory device. The memory device includes an array of memory cells, a row access circuit coupled to the array of memory cells, a column access circuit coupled to the array of memory cells, an address decoder circuit coupled to the row access circuit and the column access circuit, and a clock generator for generating an internal clock signal for synchronizing access commands to the array of memory cells. The clock generator includes an input buffer for receiving an external clock signal and a one-shot circuit coupled to the input buffer for providing output pulses in response to the external clock signal. The one-shot circuit includes a NAND SR latch having a set input, a reset input and an output. The set input is coupled to an output of the input buffer and the internal clock signal is provided on the output of the SR latch as a series of output pulses. The one-shot circuit further includes a delay circuit having an input and an output. The output of the delay circuit is coupled to the reset input of the SR latch. The input of the delay circuit is coupled to receive a first logic level indicative of a completion of an output pulse of the internal clock signal and to receive a second logic level indicative of a beginning of an output pulse of the internal clock signal. The delay circuit includes at least two delay elements coupled in series between the input and the output of the delay circuit and having a predetermined delay time, and at least two bypasses. Each bypass is associated with one delay element in a one-to-one relationship. Furthermore, each bypass is activated in response to the first logic level, thereby passing the first logic level across each delay element substantially without delay, and deactivated in response to the second logic level, thereby passing the second logic level from the input of the delay circuit to the output of the delay circuit at a time delta substantially equal to or greater than the predetermined delay time of the at least two delay elements.
For a still further embodiment, the invention provides a synchronous flash memory device. The synchronous flash memory device includes a plurality of memory banks containing non-volatile flash memory cells and a command execution logic coupled to the plurality of memory banks for receiving at least a system clock input signal and for generating commands to control operations performed on the plurality of memory banks, wherein the commands are synchronized to an internal clock signal generated from the system clock input signal by a clock generator. The clock generator includes an input buffer for receiving the system clock input signal as an external clock signal and a one-shot circuit coupled to the input buffer for providing the internal clock signal in response to the external clock signal. The one-shot circuit includes a delay circuit having at least one delay element and at least one associated bypass. The one-shot circuit generates a first logic level in response to a completion of an output pulse of the internal clock signal and presents the first logic level to an input of the delay circuit. The first logic level activates the at least one associated bypass and propagates across each delay element substantially without delay. The one-shot circuit further generates a second logic level in response to a beginning of an output pulse of the internal clock signal and presents the second logic level to the input of the delay circuit. The second logic level deactivates the at least one associated bypass and is passed to the output of the delay circuit at a time delta equal to or greater than a predetermined delay time of the at least one delay element.
For yet another embodiment, the invention provides a method of generating output pulses of an internal clock signal in response to an external clock signal. The method includes applying a first signal indicative of the external clock signal to a set input of an SR latch and generating output pulses of the internal clock signal on an output of the SR latch in response to signals applied to the set input and a reset input of the SR latch. An output pulse begins in response to a falling edge of the first signal applied to the set input, and the output pulse is completed in response to a falling edge of a second signal applied to the reset input. The method further includes generating a first logic level indicative of a completion of an output pulse of the internal clock signal and generating a second logic level indicative of a beginning of an output pulse of the internal clock signal. The method still further includes applying the first and second logic levels to an input of a delay circuit having at least one delay element and at least one bypass where each delay element has an associated bypass. Each bypass is activated in response to the first logic level applied to the input of the delay circuit, thereby bypassing each delay element and passing the first logic level to an output of the delay circuit substantially without delay. Each bypass is deactivated in response to the second logic level applied to the input of the delay circuit, thereby allowing the second logic level to propagate through each delay element and passing the second logic level to the output of the delay circuit at a time delta substantially equal to a predetermined delay time of the at least one delay element. The method further includes applying the logic level from the output of the delay circuit to a reset input of the SR latch as the second signal.
For still another embodiment, the invention provides a delay circuit. The delay circuit includes at least one delay element coupled in series, and at least one bypass associated with each delay element. The input of each bypass is coupled to the input of its associated delay element and the output of each bypass is coupled to the output of its associated delay element. Each bypass has a first pass gate coupled between its input and output. Each first pass gate is activated in response to a first logic level presented at the input of the delay circuit and deactivated in response to a second logic level presented at the input of the delay circuit.
The invention fixer provides methods and apparatus of varying scope.